CPU Deep Idle Keyword [PSARC/2008/663 Self Review]
Randy Fishel
randyf at sac.sfbay.sun.com
Tue Oct 28 14:09:35 PDT 2008
I am sponsoring the following case for Bill Holler. We believe that this
is a Self Review, but are willing to change it to a fasttrack if someone
desires. The added keywords are committed and the binding is Patch/Micro.
Template Version: @(#)sac_nextcase %I% %G% SMI
This information is Copyright 2008 Sun Microsystems
1. Introduction
1.1. Project/Component Working Name:
CPU Deep Idle Keyword
1.2. Name of Document Author/Supplier:
Author: Randy Fishel
1.3 Date of This Document:
28 October, 2008
4. Technical Description
Copyright 2008 Sun Microsystems
1. Introduction
1.1. Project/Component Working Name: cpu_deep_idle Keyword
1.2. Name of Document Author/Supplier: Bill Holler
1.3. Date of This Document: 10/20/2008
1.4. Name of Major Document Customer(s)/Consumer(s): PSARC
1.5. Email Aliases:
1.5.1. Responsible Manager: darrin.johnson at sun.com
1.5.2. Responsible Engineer: bill.holler at sun.com
1.5.4. Interest List: tesla-dev at opensolaris.org
2. Project Summary
2.1. Project Description:
Solaris support for the cpu_deep_idle keyword in power.conf(4).
A mechanism is desired to disable the default use of idle processor
power-saving features such as ACPI processor C-States beyond C1.
2.2. Risks and Assumptions:
Very few customers will use this keyword. Most customers will
desire power saving hardware idle features to be the default.
3. Business Summary
3.1. Problem Area:
There should be a mechanism to disable advanced idle-processor
power saving features. For example, next generation X86
processor hardware will support ACPI C-States beyond C1. These
C-States may have more wakeup latency from halted state than
the current C1 halt state used by Solaris. Some Deep C-States
may flush processor caches which will cause reduced performance
in some cases. The performance loss will only occur when CPUs
are idle. Other processors may incorporate similar idle power
saving features in the future.
Some customers may wish to obtain the maximum performance from
their Solaris systems at the expense of power consumption.
Solaris may be at a competitive performance disadvantage with
other Operating Systems which may be able to disable this
hardware feature.
3.3. Business Justification:
Some customers are not willing to accept any performance loss
even if the performance loss is from substantial power savings.
3.4. Competitive Analysis:
Solaris will be at a performance disadvantage compared to
other operating systems with the ability to disable hardware
power savings.
3.5. Opportunity Window/Exposure:
Now.
3.6. How will you know when you are done?:
X86 processors will not enter ACPI C-States beyond C1 when the
cpu_deep_idle keyword is set to "disable" in power.conf(4).
4. Technical Description:
4.1. Details:
pmconfig(1M) parses /etc/power.conf and passes the values to
the cpudrv driver. The cpudrv driver controls deep idle power
saving features. If the cpu_deep_idle keyword is in
power.conf(4), the cpudrv driver will use the keyword's value
to disable/enable hardware deep-idle power saving features.
Hardware deep-idle power saving features include ACPI C-States
beyond C1 (aka Deep C-States). Deep C-States will be enabled
by default.
/etc/power.conf may have [cpu_deep_idle <value>]
|
v
pmconfig
|
v
cpudrv
Applications which have extreme single-threaded performance
requirements and also frequently stop and start execution may
suffer an unacceptable performance loss with deep idle power saving
features enabled. In these rare cases the deep idle power saving
features may be disabled by adding the cpu_deep_idle keyword to
power.conf(4) with a setting of disable.
4.2. Bug/RFE Number(s): 6700904
4.4. Out of Scope:
Implementation of Deep C-State support is not in the scope of
this case.
4.5. Interfaces:
This project will import these existing interfaces.
Interface stability will be "committed".
Import:
power.conf(4) (PSARC/1992/202)
pmconfig(1m) (PSARC/1992/202)
Export:
cpu_deep_idle
cpu_deep_idle keyword.
Some systems may wish to disable idle processor power saving features
due to unavoidable increased idle CPU wakeup latency.
A cpu_deep_idle entry can be added to power.conf(4) to disable
idle processor power saving hardware features. If this entry is
present and set to default or it is not present then the default
idle processor power saving support will be used. The default
behavior will enable ACPI Deep C-States on all X86 systems which
have an invariant TSC and the ability to wake the processors from
Deep C-State. If cpu_deep_idle is present and set to disable then
Deep C-States will not be used on X86 systems.
power.conf(4) man page addition:
If supported by the platform, a cpu_deep_idle entry may be used
to enable or disable automatic use of power saving cpu idle states.
The format of the cpu_deep_idle entry is cpu_deep_idle behavior.
Acceptable behavior values are:
default Advanced cpu idle power saving features will be
enabled on hardware which supports it. On X86 systems
this may translate to the use of ACPI C-States beyond C1.
enable Enables the system to automatically use idle cpu power
saving features.
disable The system does not automatically use idle cpu power
saving features. This option may be used when maximum
performance is required at the expense of power.
absent It the cpu_deep_idle keyword is absent from power.conf(4)
the behavior is the same as the default case.
+========================================================================+
|Release Binding: Patch/Micro |
| |
|Imports: |
| |
|Name Case Classification |
|------------------------------------------------------------------------|
|power.conf(4) PSARC/1992/202 Committed |
|pmconfig(1m) PSARC/1992/202 Committed |
| |
| |
|Exports: |
| |
|Name Classification Comments |
|------------------------------------------------------------------------|
|cpu_deep_idle Committed Keyword to set CPU idle power saving |
| features. On X86 systems this may |
| be ACPI C-States beyond C1. |
| Options described below. |
| |
|cpu_deep_idle options: |
|Enable Committed Option to enable |
|Disable Committed Option to disable |
|Default Committed Set default operation. |
| Default behavior is platform specific.|
+========================================================================+
4.6. Doc Impact:
power.conf man page. See above.
4.7. Admin/Config Impact:
Administrators of systems where maximum performance is more
important than power/performance can disable this feature.
It is not anticipated than many customers will choose to disable
this feature as it provides improved power/performance.
4.8. HA Impact: None.
4.9. I18N/L10N Impact: No.
4.10. Packaging & Delivery:
All changes are to existing components and have no effect on
packaging or delivery.
4.11. Security Impact: None.
4.12. Dependencies: None
5. Reference Documents:
Advanced Configuration and Power Interface:
http://www.acpi.info/
IA-PC HPET (High Precision Event Timers) Specification:
http://www.intel.com/hardwaredesign/hpetspec_1.pdf
6. Resources and Schedule:
6.1. Projected Availability: Fall 2008
6.4. Product Approval Committee requested information:
6.4.3. Type of CPT Review and Approval expected: BugFix/RFE
6.4.5. Is this a necessary project for OEM agreements: No.
6.4.7. Target RTI Date/Release:
RTI around onnv_103 and S10U8
6.4.8. Target Code Design Review Date: 09/22/2008
6.4.9. Update approval addition: No.
6.5. ARC review type: SelfReview
7. Prototype Availability:
7.1. Prototype Availability:
Prototype available in Tesla repository in October 2008.
6. Resources and Schedule
6.4. Steering Committee requested information
6.4.1. Consolidation C-team Name:
ON
6.5. ARC review type: Automatic
6.6. ARC Exposure: open
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